Nowadays, all signal propagations among semiconductor chips such as LSIs (large scale integrated circuits) rely upon electric signals via interconnections on a substrate. However, with recent trends in higher functionalization of MPU, volume of data transmission among the chips has extremely increased, and this has raised various high-frequency-related problems. Representative problems include RC signal delay, impedance mismatching, EMC/EMI, crosstalk and the like.
In order to solve the above-described problems, various techniques such as optimization of interconnect arrangement, development of new materials and so forth have been adopted to the solution, mainly contributed by mounting-related industries.
However in recent years, effects of the above-described optimization of interconnect arrangement and development of new materials have been approaching more closer to the physical limit, so that there has arisen a need of re-examining structure per se of printed wiring board on the premise of simple mounting of semiconductor chips, in view of realizing a more advanced system functionalization. In recent years, various radical measures have been proposed in order to solve these problems. Representative examples thereof will be listed below.
Micro-Interconnect Coupling using Multi-Chip Module (MCM)
Highly functionalized chips are mounted on a precision mounting board composed of ceramic, silicon or the like, to thereby realize micro-interconnect coupling which cannot be formed on a mother board (multi-layered printed board). This configuration can narrow interconnect pitch, wherein widening of bus can drastically increase volume of data to be sent or to be received.
Electric Interconnect Coupling by Encapsulation and Integration of Various Semiconductor Chips
Various semiconductor chips are two-dimensionally encapsulated and integrated using polyimide resin or the like, and are coupled by micro-interconnects on thus-integrated board. This configuration can narrow interconnect pitch, wherein widening of bus can drastically increase volume of data to be sent or to be received.
Three-Dimensional Coupling of Semiconductor Chips
The individual semiconductor chips are provided with penetrative electrodes, and bonded to each other to thereby obtain a stacked structure. This configuration can physically shorten connection between different semiconductor chips, and can consequently avoid problems in signal delay and the like. On the other hand, the configuration raises problems in increase in the amount of heat generation and thermal stress between the semiconductor chips, ascribable to the stacking.
In order to realize still higher speed and larger volume of signal sending/receiving and larger volume as described in the above, coupling technologies based on optical transmission have been developed (see, for example, Nikkei Electronics “Encounter with Optical Interconnect”, Dec. 3, 2001, p. 122, p. 123, p. 124, p. 125, FIG. 4, FIG. 5, FIG. 6, FIG. 7; and NTT R&D, Vol. 48, No. 3, pp. 271-280 (1999), described later). The optical interconnect is applicable to various sites such as between electronic instruments, between boards inside electronic instruments, between chips on the board, and the like.
For example, as shown in FIG. 10A to FIG. 10C, on a printed circuit board 50 having an optical waveguide 51 formed thereon, a beam (laser beam, for example) modulated based on signals by emitting optics (surface emission laser, for example) 52 is allowed to enter the optical waveguides 51, the incident light is guided through the optical waveguide 51, emitted from the optical waveguide 51, and received by receiving optics (photodiode, for example) 53. In this way, it is made possible to build up an optical transmission/communication system using the optical waveguide 51 as a transmission path for laser beam or the like modulated based on signals.
The optical waveguide 51 is composed of cladding layers 60 and 61, core layers 57 held therebetween, and has lens components provided on the cladding layer 60 at positions corresponded to the light input/output portions. As shown in FIG. 10B, a plurality of core layers 57 are provided in parallel. FIG. 10B does not illustrate the cladding layer 61.
Each of the emitting optics 52 and the receiving optics 53 are disposed on bases 56a and 56b, respectively, as being corresponded to the input/output portions of the plurality of the core layers 57, to thereby configure an emitting optics array 62 and a receiving optics array 63. Each of the emitting optics 52 and the receiving optics 53 have an optical component 59 provided thereon, thereby allowing efficient emission and input of the light. In addition, the emitting optics array 62 and the receiving optics 53 are mounted on a mounting board (interposer, for example) 54 having a drive circuit element 55 formed thereon.
As shown in FIG. 10C, each of the emitting optics 52 is connected with an external connection terminal 64, and they are arranged in parallel on the base 56a as being corresponded to the individual light input/output portions of the core layers 57, to thereby configure the emitting optics array 62. The same will apply also to the receiving optics array 63.